■ Major Research Achievements

High-performance Pipelined Analog-to-Digital Converters (ADCs)

    • Background capacitor trimming technique for high-accuracy residue amplifier with zero-forcing feedback loop
    • Opamp reusing technique for low-power residue amplifiers
    • Reference-free pipelined ADC
    • Replica driving technique for low-power residue amplification

High-performance Successive Approximation Register (SAR) ADC Architectures and Design Techniques

    • Digital error correction scheme for speed-enhanced SAR ADCs
    • Nonbinary multi-bit/cycle SAR ADC architectures for performance robustness
    • Flash-assisted time-interleaved SAR ADC architectures
    • SAR-assisted time-interleaved SAR ADC with low-noise comparator

Low-power Flash ADCs

    • Interpolation techniques for reduced number of comparators

Compact-sized Digital-to-Analog Converters (DACs)

    • Switched-current cyclic DAC
    • Size-efficient column driver with switched-capacitor interpolation DAC
    • Stacked unit cell structured high-speed DAC

Design Techniques for Time-interleaved Architectures

    • Sign-equality based timing-skew calibration scheme
    • Gain-error-free digital linearity calibration for high-resolution SAR ADC

Readout Circuits for Resistive Memories

    • Logarithmic two-step ADCs with narrow-pitched column-parallel structure

Low-power CMOS Image Sensors

    • Power saving delta-readout technique inspired by the image property