MSICL


Mixed Signal Integrated Circuits Lab.

혼성신호 집적회로 연구실

LATEST NEWS

2024 NEWS
2023 NEWS
"A 25kHz-BW 97.4dB-SNDR 100.2dB-DR 3rd-order SAR-Assisted CT DSM with 1-0 MASH and DNC."
" An 81.2dB-SNDR Dual-Residue Pipeline ADC with a 2nd-Order Noise-Shaping Interpolating SAR ADC ."
" A 12-bit 1GS/s Current-Steering DAC with Paired Current Source Switching Background Mismatch Calibration ."
2022 NEWS
" A 4th-Order Continuous-Time Delta-Sigma Modulator with Hybrid Noise-Coupling ."
" A 4th-Order Continuous-Time Delta-Sigma Modulator with Hybrid Noise-Coupling ."
" A Relative-Prime Rotation Based Fully On-Chip Background Skew Calibration for Time-Interleaved ADCs ."
" A 7-bit Two-Step Flash ADC With Sample-and-Hold Sharing Technique ."
2021 NEWS
" MixedNet: Network Design Strategies For Cost-Effective Quantized CNNs ."
" A 4th-Order CT I-DSM with Digital Noise Coupling and Input Pre-Conversion Method for Initialization ."
" An Input-Buffer Embedding Dual-Residue Pipelined-SAR ADC with Nonbinary Capacitive Interpolation ."
" Youtube Live Streaming Link (Click) ."
" SSCS DL Program Link ."
2020 NEWS
" An 8-bit 1-GS/s Asynchronous Loop-Unrolled SAR-Flash ADC with Complementary Dynamic Amplifiers in 28-nm CMOS ."
" An 8b 1GS/s 2.55mW SAR-Flash ADC with Complementary Dynamic Amplifiers ."
" Compact Mixed-Signal Convolutional Neural Network Using a Single Modular Neuron ."
" A Single-Supply CDAC-Based Buffer-Embedding SAR ADC with Skip-Reset Scheme having Inherent Chopping Capability ."
" A 28-nm CMOS 12-bit 250-MS/s Voltage-Current-Time Domain 3-Stage Pipelined ADC ."
" An 8b 1GS/s 2.55mW SAR-Flash ADC with Complementary Dynamic Amplifiers ."
" A 40nm CMOS 12b 120MS/s Nonbinary SAR-assisted SAR ADC with Double Clock-Rate Coarse Decision ."
2019 NEWS
" A Single-Supply Buffer-Embedding SAR ADC with Skip-Reset having Inherent Chopping Capability ."
" A Single-Supply Buffer-Embedding SAR ADC with Skip-Reset having Inherent Chopping Capability ."
" A 9.1-ENOB 6-mW 10-bit 500-MS/s Pipelined-SAR ADC with Current-Mode Residue Processing in 28-nm CMOS ."
" A 40nm CMOS 7b 32GS/s SAR ADC with Background Channel Mismatch Calibration ."
" A 40nm CMOS 12b 200MS/s Single-amplifier Dual-residue Pipelined-SAR ADC ."
" A 6b 28GS/s Four-channel Time-interleaved Current-Steering DAC with Background Clock Phase Calibration ."
2018 NEWS
" A 18.5nW 12-bit 1-kS/s Reset-energy Saving SAR ADC for Bio-Signal Acquisition in 0.18um CMOS ."
" A 65-nm CMOS 6-Bit 20 GS/s Time-Interleaved DAC With Full-Binary Sub-DACs ." 
A 2.7-M Pixels 64-mW CMOS Image Sensor With Multicolumn-Parallel Noise-Shaping SAR ADCs ." 
2017 NEWS
" A Dual-Imaging Speed-Enhanced CMOS Image Sensor for Real-Time Edge Image Extraction ."
" Power-efficient flash ADC with complementary voltage-to-time converter."
" Normalized-Full-Scale-Referencing Digital-Domain Linearity Calibration for SAR ADC ."
2016 NEWS
" A Delta-Readout Scheme for Low-Power CMOS Image Sensors With Multi-Column-Parallel SAR ADCs ."
" A Low-Power TDC-Configured Logarithmic Resistance Sensor for MLC PCM Readout ."

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