Publications

Kent Edrian Lozada, Il-Hoon Jang, Gyeom-Je Bae, Dong-Hun Lee, Ye-Dam Kim, Hankyu Lee, Seong Joong Kim, and Seung-Tak Ryu, "A 4th-Order Continuous-Time Delta-Sigma Modulator with Hybrid Noise-Coupling," IEEE TCAS-II, 2022.

Dong-Ryeol Oh, Min-Jae Seo, and Seung-Tak Ryu, "A 7-bit Two-Step Flash ADC With Sample-and-Hold Sharing Technique," IEEE, JSSC, 2022.

Dong-Jin Chang, Byeong-Gyu Nam, and Seung-Tak Ryu, "MixedNet: Network Design Strategies For Cost-Effective Quantized CNNs," IEEE, Access, 2021. 

Dong-Jin Chang, Michael Choi, and Seung-Tak Ryu, "A 28-nm 10-b 2.2-GS/s 18.2-mW Relative-Prime Time-Interleaved Sub-ranging SAR ADC with On-Chip Background Skew Calibration," IEEE, JSSC, 2021.

Dong-Ryeol Oh, Kyoung-Jun Moon, Won-Mook Lim, Ye-Dam Kim, Eun-Ji An, and Seung-Tak Ryu, "An 8-bit 1-GS/s Asynchronous Loop-Unrolled SAR-Flash ADC with Complementary Dynamic Amplifiers in 28-nm CMOS," IEEE, JSSC, 2020.

Dong-Jin Chang, Byeong-Gyu Nam, and Seung-Tak Ryu, "Compact Mixed-Signal Convolutional Neural Network Using a Single Modular Neuron," IEEE TCAS-I, 2020.

Min-Jae Seo, Dong-Hwan Jin, Ye-Dam Kim, Jong-Pal Kim, and Seung-Tak Ryu, "A Single-Supply CDAC-Based Buffer-Embedding SAR ADC with Skip-Reset Scheme having Inherent Chopping Capability," IEEE JSSC, 2020.

Kyoung-Jun Moon, Dong-Ryeol Oh, Michael Choi, and Seung-Tak Ryu, "A 28-nm CMOS 12-bit 250-MS/s Voltage-Current-Time Domain 3-Stage Pipelined ADC," IEEE TCAS-II, 2020.

Yi-Ju Roh, Dong-Jin Chang, and Seung-Tak Ryu, "A 40nm CMOS 12b 120MS/s Nonbinary SAR-assisted SAR ADC with Double Clock-Rate Coarse Decision," IEEE TCAS-II, 2020.

Kyoung-Jun Moon, Dong-Shin Jo, Wan Kim, Michael Choi, Hyung-Jong Ko, and Seung-Tak Ryu, "A 9.1-ENOB 6-mW 10-bit 500-MS/s Pipelined-SAR ADC with Current-Mode Residue Processing in 28-nm CMOS," IEEE JSSC, 2019.

Dong-Shin Jo, Ba-Ro-Saim Sung, Min-Jae Seo, Woo-Cheol Kim and Seung-Tak Ryu, "A 40nm CMOS 7b 32GS/s SAR ADC with Background Channel Mismatch Calibration," IEEE TCAS-II, 2019.

Dong-Hwan Jin, Ji-Wook Kwon, Min-Jae Seo , Mi-Young Kim, Min-Chul Shin, Seok-Joon Kang, Jung-Hyuk Yoon, Taek-Seung Kim, and Seung-Tak Ryu, "A Reference-Free Temperature-Dependency-Compensating Readout Scheme for Phase-Change Memory Using Flash-ADC-Configured Sense Amplifiers," IEEE JSSC, 2019.

Dong-Ryeol Oh, Jong-In Kim, Dong-Shin Jo, Woo-Chul Kim, Dong-Jin Chang, and Seung-Tak Ryu, “A 65-nm CMOS 6-bit 2.5-GS/s 7.5-mW 8x Time-Domain Interpolating Flash ADC with Sequential Slope-Matching Offset Calibration,” IEEE JSSC, 2018.

Min-Jae Seo, Dong-Hwan Jin, Ye-Dam Kim, Sun-Il Hwang, Jong-Pal Kim and Seung-Tak Ryu, “A 18.5nW 12-bit 1-kS/s Reset-energy Saving SAR ADC for Bio-Signal Acquisition in 0.18um CMOS,” IEEE TCAS-I, 2018.

Min-Jae Seo, Yi-Ju Roh, Dong-Jin Chang, Wan Kim, Ye-Dam Kim and Seung-Tak Ryu, “A Reusable Code-based SAR ADC Design With CDAC Compiler and Synthesizable Analog Building Blocks,” IEEE TCAS-II, 2018.

Hyun-Wook Kang, Hyeok-Ki Hong, Wan Kim, and Seung-Tak Ryu, “A Time-Interleaved 12-b 270-MS/s SAR ADC With Virtual-Timing-Reference Timing-Skew Calibration Scheme,” IEEE JSSC, 2018.

Si-Nai Kim, Woo-Cheol Kim, Min-Jae Seo, and Seung-Tak Ryu, “A 65-nm CMOS 6-Bit 20 GS/s Time-Interleaved DAC With Full-Binary Sub-DACs,” IEEE TCAS-II, 2018.

Sun-Il Hwang, Jae-Hyun Chung, Hyeon-June Kim, Il-Hoon Jang, Min-Jae Seo, Sang-Hyun Cho, Heewon Kang, Minho Kwon, and Seung-Tak Ryu, “A 2.7-M Pixels 64-mW CMOS Image Sensor With Multicolumn-Parallel Noise-Shaping SAR ADCs,” IEEE TED, 2018.

Il-Hoon Jang, Min-Jae Seo, Mi-Young Kim, Jae-Keun Lee, Seung-Yeob Baek, Sun-Woo Kwon, Michael Choi, Hyung-Jong Ko, and Seung-Tak Ryu, “A 4.2-mW 10-MHz BW 74.4-dB SNDR Continuous-Time Delta-Sigma Modulator With SAR-Assisted Digital-Domain Noise Coupling,” IEEE JSSC, 2018.

Dong-Jin Chang, Min-Jae Seo, Hyeok-Ki Hong, Seung-Tak Ryu, “A 65 nm 0.08-to-680 MHz Low-Power Synthesizable MDLL With Nested-Delay Cell and Background Static Phase Offset Calibration,” IEEE TCAS-II, 2018.

Hyeon-June Kim, Sun-Il Hwang, Jae-Hyun Chung, Jong-Ho Park, and Seung-Tak Ryu, “A Dual-Imaging Speed-Enhanced CMOS Image Sensor for Real-Time Edge Image Extraction,” IEEE JSSC, 2017.

D.-R. Oh, D.-S. Jo, K.-J. Moon, Y.-J. Roh, and S.-T. Ryu, “Power-efficient flash ADC with complementary voltage-to-time converter,” IET Electronics Letters, 2017.

Dong-Jin Chang, Wan Kim, Min-Jae Seo, Hyeok-Ki Hong, Seung-Tak Ryu, “Normalized-Full-Scale-Referencing Digital-Domain Linearity Calibration for SAR ADC,” IEEE TCAS-I, 2017.

Hyeon-June Kim, Sun-Il Hwang, Ji-Wook Kwon, Dong-Hwan Jin, Byoung-Soo Choi, Sang-Gwon Lee, Jong-Ho Park, Jang-Kyoo Shin, and Seung-Tak Ryu, “A Delta-Readout Scheme for Low-Power CMOS Image Sensors With Multi-Column-Parallel SAR ADCs,” IEEE JSSC, 2016.

Wan Kim, Hyeok-Ki Hong, Yi-Ju Roh, Hyun-Wook Kang, Sun-Il Hwang, Dong-Shin Jo, Dong-Jin Chang, Min-Jae Seo, and Seung-Tak Ryu, “A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC,” IEEE JSSC, 2016.

Ji-Wook Kwon, Dong-Hwan Jin, Hyeon-June Kim, Sun-Il Hwang, Min-Chul Shin, Jun-Ho Cheon, and Seung-Tak Ryu, “A Low-Power TDC-Configured Logarithmic Resistance Sensor for MLC PCM Readout,” IEEE Sensors Journal, 2016.

Hyun-Wook Kang, H.-K. Hong, S. Park, K.-J. Kim, K.-H. Ahn, and S.-T. Ryu, “A Sign-Equality-Based Background Timing-Mismatch Calibration Algorithm for Time-Interleaved ADCs,” IEEE TCAS-II, 2016.

A. Ramadoss, K.-N. Kang, H.-J. Ahn, S.-I. Kim, S.-T. Ryu, and J.-H. Jang, “Realization of high performance flexible wire supercapacitors based on 3-dimensional NiCo2O4/Ni fibers,” Journal of Materials Chemistry A, 2016.

Si-Nai Kim, Mee-Ran Kim, Ba-Ro-Saim Sung, Hyun-Wook Kang, Min-Hyung Cho, and Seung-Tak Ryu, “A SUC-Based Full-Binary 6-bit 3.1-GS/s 17.7-mW Current-Steering DAC in 0.038 mm2,” IEEE TVLSI, 2016.

W.-C. Kim, W.-C. Kim, J.-G. Kim, K.-H. Ahn, G.-J. Kim, S.-H. Park and S.-T. Ryu, “Calibration-spur reduction in current-steering DAC utilising digital-and-analogue hybrid return-to-zero (HRZ) method,” IET Electronics Letters, 2015. 

H.-W. Kang, H.-K. Hong, S. Park, K.-J. Kim, K.-H. Ahn, and S.-T. Ryu, “Ternary-level thermometer C-DAC switching scheme for flash-assisted SAR ADCs,” IEICE Electronics Express, 2015.

Jong-In Kim, Dong-Ryeol Oh, Dong-Shin Jo, Ba-Ro-Saim Sung and Seung-Tak Ryu, “A 65 nm CMOS 7b 2 GS/s 20.7 mW Flash ADC With Cascaded Latch Interpolation,” IEEE JSSC, 2015.

Dong-Hwan Jin, Ji-Wook Kwon, Hyeon-June Kim, Sun-Il Hwang, Minchul Shin, Junho Cheon, and Seung-Tak Ryu, “A 15 µm-Pitch, 8.7-ENOB, 13-Mcells/sec Logarithmic Readout Circuit for Multi-Level Cell Phase Change Memory,” IEEE JSSC, 2015.

Hyeok-Ki Hong, Wan Kim, Hyun-Wook Kang, Sun-Jae Park, Michael Choi, Ho-Jin Park, and Seung-Tak Ryu, “A Decision-Error-Tolerant 45 nm CMOS 7b 1 GS/s Nonbinary 2b/Cycle SAR ADC,” IEEE JSSC, 2015.

H. S. Kim, J. H. Yang, S. H. Park, S. T. Ryu, and G. H. Cho, “A 10-Bit Column-Driver IC With Parasitic-Insensitive Iterative Charge-Sharing Based Capacitor-String Interpolation for Mobile Active-Matrix LCDs,” IEEE JSSC, 2014.

Ghil-Geun Oh, C. K. Lee, and S. T. Ryu, “A 10-Bit 40-MS/s Pipelined ADC With a Wide Range Operating Temperature for WAVE Applications,” IEEE TCAS-II, 2014.

Chang-kyo Lee, W. Kim, H. Kang, and S. T. Ryu, “A Replica-Driving Technique for High Performance SC Circuits and Pipelined ADC Design,” IEEE TCAS-I, 2013.

Seung-Yeob Baek, J. K. Lee, and S. T. Ryu, “An 88-dB Max-SFDR 12-bit SAR ADC With Speed-Enhanced ADEC and Dual Registers,” IEEE TCAS-II, 2013.

Jun-Hyeok Yang, Seung-Chul Jung, Young-Suk Son, Seung-Tak Ryu, and Gyu-Hyeong Cho, “A Noise-Immune High-Speed Readout Circuit for In-Cell Touch Screen Panels,” IEEE TCAS-I, 2013.

Jong-In Kim, B. Sung, W. Kim, and S. T. Ryu, “A 6-b 4.1-GS/s Flash ADC With Time-Domain Latch Interpolation in 90-nm CMOS,” IEEE JSSC, 2013.

H. S. Kim, S. W. Han, J. H. Yang, S. Kim, Y. Kim, D. K. Yoon, J. S. Lee, J. C. Park, Y. Sung, S. D. Lee, S. T. Ryu, and G. H. Cho, "An Asynchronous Sampling-Based 128 x 128 Direct Photon-Counting X-Ray Image Detector with Multi-Energy Discrimination and High Spatial Resolution," IEEE JSSC, 2013.

J. P. Im, S. W. Wang, S. T. Ryu, and G. H. Cho, "A 40 mV Transformer-Reuse Self-Startup Boost Converter With MPPT Control for Thermoelectric Energy Harvesting," IEEE JSSC, 2012.

So-Young Kang, Seung-Tak Ryu, and Chul-Soon Park, “A Precise Decibel-Linear Programmable Gain Amplifier Using a Constant Current-Density Function,” IEEE Transactions on Microwave Theory and Techniques, 2012.

Kiuk Gwak, Sang-Gug Lee, and Seung-Tak Ryu, “Improved Charge Pump with Reduced Reverse Current,” Journal of Semiconductor Technology and Science, 2012. 

Si-Nai Kim, Wan Kim, Chang-Kyo Lee, and Seung-Tak Ryu, “A 6-bit 3.3-GS/s Current-Steering DAC with Stacked Unit Cell Structure,” Journal of Semiconductor Technology and Science, 2012.

Hun-Do Shin and Seung-Tak Ryu, “A 180-uW, 120-MHz, 4th-order Low-Pass Bessel Filter Based on FVF Biquad,” IEICE Transactions on Electronics, 2012.

Hun-Do Shin and Seung-Tak Ryu, “Bandwidth-Power Optimization Methodology for SFB filter Design,” Journal of Semiconductor Technology and Science, 2012.

Huy-Binh Le, Sang-Gug Lee and Seung-Tak Ryu, “A Single-supply 84dB DR Audio-band ADC for Compact Digital Microphones,” IEICE Transactions on Electronics, 2012.

Sang-Hyun Cho, Chang-Kyo Lee, Sang-Gug Lee, and Seung-Tak Ryu, “A Two-Channel Asynchronous SAR ADC With Metastable-Then-Set Algorithm,” IEEE TVLSI, 2012.

Hyun-Sik Kim, Jin-Yong Jeon, Sung-Woo Lee, Jun-Hyeok Yang, Seung-Tak Ryu and Gyu-Hyeong Cho, “A Compact-Sized 9 Bit Switched-Current DAC for AMOLED Mobile Display Drivers,” IEEE TCAS-II, 2011.

Ji-Wook Kwon and Seung-Tak Ryu, “An Inherently dB-Linear All-CMOS Variable Gain Amplifier,” Journal of Semiconductor Technology and Science, 2011.

Huy-Binh Le, Xuan-Dien Do, Sang-Gug Lee and Seung-Tak Ryu, “A long Reset-time Power-on Reset Circuit with Brown-out Detection Capability,” IEEE TCAS-II, 2011.

Sang-Hyun Cho, Chang-Kyo Lee, Jong-Kee Kwon, and Seung-Tak Ryu, “A 550-μW 10-b 40-MS/s SAR ADC With Multistep Addition-Only Digital Error Correction,” IEEE JSSC, 2011.

Yeong-Shin Jang, Hoai-Nam Nguyen, Seung-Tak Ryu and Sang-Gug Lee, “Yield-Ensuring DAC-embedded Opamp design based on accurate behavioral model development,” IEICE Transactions on Electronics, 2010.

S.H.Cho, H.D. Lee, K.D. Kim, S.T. Ryu and J.K. Kwon, “Dual-mode VCO gain topology for reducing in-band noise and reference spur of PLL in 65nm CMOS,” IET Electronics Letters, 2010.

S.-H. Cho, C.-K. Lee, B.-R.-S. Sung and S.-T. Ryu, “Digital Error Correction Technique for Binary Decision Successive Approximation ADCs,” IET Electronics Letters, 2009.

Huy-Binh Le, Seung-Tak Ryu and Sang-Gug Lee, “A Fully On-Chip Gm-Opamp-RC Based Preamplifier for Electret Condenser Microphones,” IEICE Transactions on Electronics, 2009.

H. B. Le, J. W. Nam, S. T. Ryu and S. G. Lee, “Single-Chip A/D Converter for Digital Microphones with On-Chip Preamplifier and Time-Domain Noise Isolation,” IET Electronics Letters, 2009.

Seung-Tak Ryu, Bang-Sup Song, and Kanti Bacrania, “A 10-bit 50-MS/s Pipelined ADC With Opamp Current Reuse,” IEEE JSSC, 2007.