MSICL

Mixed Signal Integrated Circuits Lab.

혼성신호 집적회로 연구실

LATEST NEWS

2024 NEWS

[2024.10] Ji-Wook Kwon's paper has been accepted to TCAS-II.

"An M-Metric Readout Circuit for MLC Phase-Change Memory with a Comparator-Based Push-Pull Bit-Line Driver."

[2024.10] Charlie Tahar's paper has been accepted to IEEE Transactions on Nuclear Science, on the Special Issue on NSREC 2024.

"12-bit High-Voltage Current-Steering-Assisted R-2R DAC with RCM and Parallel Switch for Satellite-Applications ."

[2024.10] Lizhen Zhang's paper has been accepted to IEEE Open Journal of Circuits and Systems 2024.

"DR Loss-Free Dithering-Based Digital Background Linearity Calibration for SAR-Assisted Multi-Stage ADCs with Digital Input-Interference Cancellation ."

[2024.09] Kent Edrian Lozada's paper has been invited and accepted to IEEE Open Journal of the Solid-State Circuits Society 2024.

"SAR-Assisted Energy-Efficient Hybrid ADCs ."

[2024.08] Charlie Tahar's paper has been accepted to IEEE Asian Solid-State Circuits Conference 2024.

"TID-Tolerant StrongARM Comparator and Sampling Network for Satellite Application High-Voltage ADCs ."

[2024.08] Bo Gao's paper has been accepted to IEEE Asian Solid-State Circuits Conference 2024.

"A 28nm CMOS 12-bit-600-MS/s 15.6mW Pipelined ADC with Two-Stage Gainboosting FIA-based RA ."

[2024.08] Lizhen Zhang's paper has been accepted to IEEE Asian Solid-State Circuits Conference 2024.

"A 5x OSR 1MHz-BW 81dB-SNDR 5th-Order Noise-Shaping SAR ADC with Zero-Optimized 3rd-Order Integrator ."

[2024.07] Kent Edrian Lozada's paper has been invited to JSSC, on the Special Issue on VLSI Circuits Symposium 2024.

[2024.05] Charlie Tahar received the 2024 NSREC Early Career Travel Grant Award.

[2024.04] Kent Edrian Lozada and Dong-Hun Lee's paper has been accepted to JSSC, on the Special Issue on A-SSCC 2023.

"A 25kHz-BW 97.4dB-SNDR SAR-Assisted Continuous-Time 1-0 MASH Delta-Sigma Modulator with Digital Noise Coupling."

[2024.04] Ye-Dam Kim's paper has been accepted to the 2024 IEEE VLSI Symposium on Technology and Circuits.

"A 100kHz-BW 99dB-DR Continuous-Time Tracking-Zoom Incremental ADC with Residue-Gain Switching and Digital NC-FF ."

[2024.04] Kent Edrian Lozada's paper has been accepted to the 2024 IEEE VLSI Symposium on Technology and Circuits.

"A 0.38mW 200kHz-BW 92.1dB-DR Single-Opamp 4th-order Continuous-Time Delta-Sigma Modulator with 3rd-order Noise Coupling ."

[2024.03] Charlie Tahar's abstract has been accepted to IEEE Nuclear & Space Radiation Effects Conference 2024.

[2024.03] Kent Edrian Lozada's presentation at the 2023 A-SSCC has been invited for a Special Session at 2024 IEEE Custom Integrated Circuits Conference.

[2024.01] Jae-Hyun Chung's paper has been accepted to JSSC.

"A 1.5-MHz BW 81.2-dB SNDR Dual-Residue Pipeline ADC With a Fully Dynamic Noise-Shaping Interpolating-SAR ADC ."

2023 NEWS

[2023.11] Kent Edrian Lozada and Dong-Hun Lee's paper has been invited to JSSC, on the Special Issue on A-SSCC 2023.

[2023.11] Kent Edrian Lozada and Dong-Hun Lee received the Distinguished Design Award at the Student Design Contest of the 2023 IEEE Asian Solid-State Circuits Conference.

[2023.08] Kent Edrian Lozada and Dong-Hun Lee's paper has been accepted to the 2023 IEEE Asian Solid-State Circuits Conference.

"A 25kHz-BW 97.4dB-SNDR 100.2dB-DR 3rd-order SAR-Assisted CT DSM with 1-0 MASH and DNC."

[2023.06] Our alumnus Dr. Dong-Jin Chang joins Chungnam National University as an assistant professor. Congratulations!

[2023.03] Our alumnus Dr. Dong-Ryeol Oh joins Jeju National University as an assistant professor. Congratulations!

[2023.02] Jae-Hyun Chung received the Special Award (IEEE SSCS Seoul Chapter) at the 30th Korean Conference on Semiconductors (KCS).

[2023.01] Jae-Hyun Chung's paper has been accepted to the 2023 IEEE Custom Integrated Circuits Conference.

" An 81.2dB-SNDR Dual-Residue Pipeline ADC with a 2nd-Order Noise-Shaping Interpolating SAR ADC ."

[2023.01] Chang-Un Park's paper has been accepted to the 2023 IEEE Custom Integrated Circuits Conference.

" A 12-bit 1GS/s Current-Steering DAC with Paired Current Source Switching Background Mismatch Calibration ."

2022 NEWS

[2022.06] Kent Edrian Lozada's paper has been invited and accepted to the TCAS-II for the Special Issue on MWSCAS 2022.

" A 4th-Order Continuous-Time Delta-Sigma Modulator with Hybrid Noise-Coupling ."

[2022.05] Kent Edrian Lozada's paper has been accepted to the 2022 IEEE International Midwest Symposium on Circuits and Systems.

" A 4th-Order Continuous-Time Delta-Sigma Modulator with Hybrid Noise-Coupling ."

[2022.04] Dong-Jin Chang's paper has been accepted to the 2022 IEEE VLSI Symposium on Technology and Circuits.

" A Relative-Prime Rotation Based Fully On-Chip Background Skew Calibration for Time-Interleaved ADCs ."

[2022.03] Dong-Ryeol Oh's paper has been accepted to JSSC.

" A 7-bit Two-Step Flash ADC With Sample-and-Hold Sharing Technique ."

[2022.02] Our alumnus Dr. Min-Jae Seo joins Gachon University (Department of Electronic Engineering) as an assistant professor. Congratulations!

2021 NEWS

[2021.12] Ye-Dam Kim and Kent Edrian Lozada received the Excellence Award at IITP-ITRC AISS Workshop.

[2021.09] Seung-Yong Lim received the Excellence Award for KAIST-SAMSUNG Industry-University Cooperation Project.

[2021.08] Dong-Jin Chang's paper has been accepted to IEEE Access.

" MixedNet: Network Design Strategies For Cost-Effective Quantized CNNs ."

[2021.08] Ye-Dam Kim's paper has been accepted to IEEE Asian Solid-State Circuits Conference 2021.

" A 4th-Order CT I-DSM with Digital Noise Coupling and Input Pre-Conversion Method for Initialization ."

[2021.08] Seungyong Lim's paper has been accepted to IEEE Asian Solid-State Circuits Conference 2021.

" An Input-Buffer Embedding Dual-Residue Pipelined-SAR ADC with Nonbinary Capacitive Interpolation ."

[2021.07] Dr. Dong-Jin Chang participated as a speaker in the Science Slam D program hosted by Daejeon MBC.

" Youtube Live Streaming Link (Click) ."

[2021.04] Prof. Ryu has been invited to serve as a Distinguished Lecturer for IEEE Solid-State Circuits Society.

" SSCS DL Program Link ."

[2021.04] Dong-Jin Chang's paper has been accepted to JSSC.

" A 28-nm 10-b 2.2-GS/s 18.2-mW Relative-Prime Time-Interleaved Sub-ranging SAR ADC with On-Chip Background Skew Calibration ."

2020 NEWS

[2020.12] Dong-Ryeol Oh's paper has been accepted to JSSC, on the Special Issue on VLSI Circuits Symposium 2020.

" An 8-bit 1-GS/s Asynchronous Loop-Unrolled SAR-Flash ADC with Complementary Dynamic Amplifiers in 28-nm CMOS ."

[2020.07] Dong-Ryeol Oh's paper has been invited to JSSC, on the Special Issue on VLSI Circuits Symposium 2020.

" An 8b 1GS/s 2.55mW SAR-Flash ADC with Complementary Dynamic Amplifiers ."

[2020.07] Dong-Jin Chang's paper has been accepted to TCAS-I.

" Compact Mixed-Signal Convolutional Neural Network Using a Single Modular Neuron ."

[2020.06] Min-Jae Seo's paper has been accepted to JSSC, on the Special Issue of the 2019 A-SSCC.

" A Single-Supply CDAC-Based Buffer-Embedding SAR ADC with Skip-Reset Scheme having Inherent Chopping Capability ."

[2020.04] Kyung-Jun Moon's paper has been accepted to TCAS-II.

" A 28-nm CMOS 12-bit 250-MS/s Voltage-Current-Time Domain 3-Stage Pipelined ADC ."

[2020.04] Dong-Ryeol Oh's paper has been accepted to the IEEE 2020 Symposium on VLSI Circuits.

" An 8b 1GS/s 2.55mW SAR-Flash ADC with Complementary Dynamic Amplifiers ."

[2020.03] Yi-Ju Roh's paper has been accepted to TCAS-II.

" A 40nm CMOS 12b 120MS/s Nonbinary SAR-assisted SAR ADC with Double Clock-Rate Coarse Decision ."

[2020.02] Kyung-Jun Roh and Ye-Dam Kim received the Best Poster Award at the 27th Korean Conference on Semiconductors (IDEC CDC).

2019 NEWS

[2019.11] Min-Jae Seo's paper has been invited to JSSC, on the Special Issue of the 2019 A-SSCC.

" A Single-Supply Buffer-Embedding SAR ADC with Skip-Reset having Inherent Chopping Capability ."

[2019.09] Ye-Dam Kim received the Best Paper Award (IEEE CASS Seoul Chapter) at the 19th Workshop on RF/Analog Circuit Technology.

[2019.08] Min-Jae Seo's paper has been accepted to IEEE Asian Solid-State Circuits Conference 2019.

" A Single-Supply Buffer-Embedding SAR ADC with Skip-Reset having Inherent Chopping Capability ."

[2019.06] Kyoung-Jun Moon's paper has been accepted to JSSC.

" A 9.1-ENOB 6-mW 10-bit 500-MS/s Pipelined-SAR ADC with Current-Mode Residue Processing in 28-nm CMOS ."

[2019.05] Dong-Shin Jo's paper has been accepted to TCAS-II.

" A 40nm CMOS 7b 32GS/s SAR ADC with Background Channel Mismatch Calibration ."

[2019.03] Min-Jae Seo's paper has been accepted to the 2019 IEEE Symposium on VLSI Circuits.

" A 40nm CMOS 12b 200MS/s Single-amplifier Dual-residue Pipelined-SAR ADC ."

[2019.03] Woo-Cheol Kim's paper has been accepted to the 2019 IEEE Symposium on VLSI Circuits.

" A 6b 28GS/s Four-channel Time-interleaved Current-Steering DAC with Background Clock Phase Calibration ."

[2019.02] Dong-Hwan Jin's paper has been accepted to JSSC.

" A Reference-Free Temperature-Dependency-Compensating Readout Scheme for Phase Change Memory Using Flash ADC Configured Sense Amplifiers."

2018 NEWS

[2018] Dong-Ryeol Oh's paper has been accepted to JSSC.

“ A 65-nm CMOS 6-bit 2.5-GS/s 7.5-mW 8x Time-Domain Interpolating Flash ADC with Sequential Slope-Matching Offset Calibration .”

[2018] Min-Jae Seo received the special (enterprise) award in The 19th Korean Semiconductor Design Competition.

[2018] Min-Jae Seo's paper has been accepted to TCAS-I.

" A 18.5nW 12-bit 1-kS/s Reset-energy Saving SAR ADC for Bio-Signal Acquisition in 0.18um CMOS ."

[2018] Min-Jae Seo's paper has been accepted to ISICAS.

" A 18.5nW 12-bit 1-kS/s Reset-energy Saving SAR ADC for Bio-Signal Acquisition in 0.18um CMOS ."

[2018] Min-Jae Seo's paper has been accepted to TCAS-II.

" A Reusable Code-based SAR ADC Design With CDAC Compiler and Synthesizable Analog Building Blocks ."

[2018] Hyun-wook Kang received the Encouragement prize, Human-Tech paper award.

[2018] Hyun-Wook Kang's paper has been accepted to JSSC.

" A Time-Interleaved 12-b 270-MS/s SAR ADC With Virtual-Timing-Reference Timing-Skew Calibration Scheme ."

[2018] Si-Nai Kim's paper has been accepted to TCAS-II.

" A 65-nm CMOS 6-Bit 20 GS/s Time-Interleaved DAC With Full-Binary Sub-DACs ."

[2018] Sun-Il Hwang's paper has been accepted to TED.

“ A 2.7-M Pixels 64-mW CMOS Image Sensor With Multicolumn-Parallel Noise-Shaping SAR ADCs ."

[2018] Il-Hoon Jang's paper has been accepted to JSSC.

" A 4.2-mW 10-MHz BW 74.4-dB SNDR Continuous-Time Delta-Sigma Modulator With SAR-Assisted Digital-Domain Noise Coupling ."

[2018] Dong-Jin Chang's paper has been accepted to TCAS-II.

" A 65 nm 0.08-to-680 MHz Low-Power Synthesizable MDLL With Nested-Delay Cell and Background Static Phase Offset Calibration ."

2017 NEWS

[2017] ll-Hoon Jang received the special (enterprise) award in The 18th Korean Semiconductor Design Competition.

[2017] Hyeon-June Kim's paper has been accepted to JSSC.

" A Dual-Imaging Speed-Enhanced CMOS Image Sensor for Real-Time Edge Image Extraction ."

[2017] Dong-Ryeol Oh's paper has been accepted to EL.

" Power-efficient flash ADC with complementary voltage-to-time converter."

[2017] Ki-Hoon Seo's paper has been accepted to MWSCAS.

" Normalized-Full-Scale-Referencing Digital-Domain Linearity Calibration for SAR ADC ."

[2017] ll-Hoon Jang's paper has been accepted to VLSI Circuits.

" A 4.2mW 10MHz BW 74.4dB SNDR Fourth-order CT DSM with Second-order Digital Noise Coupling Utilizing an 8b SAR ADC ."

[2017] Kyoung-Jun Moon's paper has been accepted to VLSI Circuits.

"A 9.1 ENOB 21.7fJ/conversion-step 10b 500MS/s Single-channel Pipelined SAR ADC with a Current-mode Fine ADC in 28nm CMOS ."

2016 NEWS

[2016] Hyeon-June Kim's paper has been accepted to JSSC.

" A Delta-Readout Scheme for Low-Power CMOS Image Sensors With Multi-Column-Parallel SAR ADCs ."

[2016] Wan Kim's paper has been accepted to JSSC.

" A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC ."

[2016] Ji-Wook Kwon's paper has been accepted to Sensors Journal.

" A Low-Power TDC-Configured Logarithmic Resistance Sensor for MLC PCM Readout ."

[2016] Si-Nai Kim's paper has been accepted to TVLSI.

" A Sign-Equality-Based Background Timing-Mismatch Calibration Algorithm for Time-Interleaved ADCs ."

CONTACT US

Office Address:

- - E3-2, 동측 4층
  - #4230/ #4224/ #4225(Prof.), East Wing, School of Electrical Engineering (E3-2), KAIST, 291 Daehak-ro, Yuseong-gu, Daejeon 34141, Republic of Korea.
  - 대전 유성구 대학로 291 (한국과학기술원), 전기및전자공학부(E3-2), 동 #4230/ #4224/ #4225(교수님).

Contact No.:

- - Students' office: +82-42-350-7625 / +82-42-350-7525
  - Professor's office: +82-42-350-7425