Publications

Kent Edrian Lozada*, Dong-Hun Lee*, Ye-Dam Kim, Ho-Jin Kim, Youngjae Cho, Michael Choi, and Seung-Tak Ryu, "A 25kHz-BW 97.4dB-SNDR 100.2dB-DR 3rd-order SAR-Assisted CT DSM with 1-0 MASH and DNC," IEEE ASSCC, 2023. (*ECAs)

Jae-Hyun Chung, Ye-Dam Kim, Chang-Un Park, Kun-Woo Park, Min-Jae Seo, and Seung-Tak Ryu, "An 81.2dB-SNDR Dual-Residue Pipeline ADC with a 2nd-Order Noise-Shaping Interpolating SAR ADC," IEEE CICC, 2023.

Chang-Un Park, Jae-Hyun Chung, and Seung-Tak Ryu, “A 12-bit 1GS/s Current-Steering DAC with Paired Current Source Switching Background Mismatch Calibration,” IEEE CICC, 2023.

Kent Edrian Lozada, Il-Hoon Jang, Gyeom-Je Bae, Dong-Hun Lee, Ye-Dam Kim, Hankyu Lee, Seong Joong Kim, and Seung-Tak Ryu, "A 4th-Order Continuous-Time Delta-Sigma Modulator with Hybrid Noise-Coupling," IEEE MWSCAS, 2022.

Dong-Jin Chang, and Seung-Tak Ryu, “A Relative-Prime Rotation Based Fully On-Chip Background Skew Calibration for Time-Interleaved ADCs,” IEEE VLSI Symposium on Technology and Circuits, 2022. 

Ye-Dam Kim, Jae-Hyun Chung, Kent Edrian Lozada, Dong-Jin Chang, and Seung-Tak Ryu, “A 4th-Order CT I-DSM with Digital Noise Coupling and Input Pre-Conversion Method for Initialization,” IEEE ASSCC, 2021.

Seungyong Lim, Raymond Mabilangan, Dong-Jin Chang, Youngjae Cho, Michael Choi, and Seung-Tak Ryu, “An Input-Buffer Embedding Dual-Residue Pipelined-SAR ADC with Nonbinary Capacitive Interpolation,” IEEE ASSCC, 2021. 

Dong-Ryeol Oh, Kyoung-Jun Moon, Won-Mook Lim, Ye-Dam Kim, Eun-Ji An, and Seung-Tak Ryu  “An 8b 1GS/s 2.55mW SAR-Flash ADC with Complementary Dynamic Amplifiers," IEEE Symposium on VLSI Circuits, 2020.

Min-Jae Seo, Dong-Hwan Jin, Ye-Dam Kim, Jong-Pal Kim, Dong-Jin Chang, Won-Mook Lim, Jae-Hyun Chung, Chang-Un Park, Eun-Ji An, and Seung-Tak Ryu, “A Single-Supply Buffer-Embedding SAR ADC with Skip-Reset having Inherent Chopping Capability,” IEEE ASSCC, 2019.

Min-Jae Seo, Ye-Dam Kim, Jae-Hyun Chung, and Seung-Tak Ryu, “A 40nm CMOS 12b 200MS/s Single-Amplifier Dual-Residue Pipelined-SAR ADC,” IEEE Symposium on VLSI Circuits, 2019.

Woo-Cheol Kim, Dong-shin Jo, Yi-Ju Roh, Ye-Dam Kim, and Seung-Tak Ryu, “A 6b 28GS/s 4-channel Time-interleaved Current-Steering DAC with Background Clock Phase Calibration ,” IEEE Symposium on VLSI Circuits, 2019. 

Min-Jae Seo, Dong-Hwan Jin, Ye-Dam Kim, Sun-Il Hwang, Jong-Pal Kim, and Seung-Tak Ryu, “A 18.5nW 12-bit 1-kS/s Reset-energy Saving SAR ADC for Bio-Signal Acquisition in 0.18um CMOS,” IEEE ISICAS, 2018. (Published in TCAS-I)

Ki-Hoon Seo, Il-Hoon Jang, Kyung-Jun Noh, and Seung-Tak Ryu, “An incremental zoom sturdy MASH ADC,” IEEE MWSCAS, 2017.

Il-Hoon Jang, Min-Jae Seo, Mi-Young Kim, Jae-Keun Lee, Seung-Yeob Baek, Sun-Woo Kwon, Michael Choi, Hyung-Jong Ko, and Seung-Tak Ryu, “A 4.2mW 10MHz BW 74.4dB SNDR Fourth-order CT DSM with Second-order Digital Noise Coupling Utilizing an 8b SAR ADC,” IEEE Symposium on VLSI Circuits, 2017.

Kyoung-Jun Moon, Hyun-Wook Kang, Dong-Shin Jo, Mi-Young Kim, Seung-Yeob Baek, Michael Choi, Hyung-Jong Ko, and Seung-Tak Ryu, “A 9.1 ENOB 21.7fJ/conversion-step 10b 500MS/s Single-channel Pipelined SAR ADC with a Current-mode Fine ADC in 28nm CMOS,” IEEE Symposium on VLSI Circuits, 2017.

Hyeon-June Kim, Sun-Il Hwang, Ji-Wook Kwon, Dong-Hwan Jin, Byoung-Soo Choi, Sang-Gwon Lee, Jong-Ho Park, Jang-Kyoo Shin, and Seung-Tak Ryu, “Delta readout scheme for image-dependent power savings in a CMOS image sensor with multi-column-parallel SAR ADCs,” IEEE ASSCC, 2015.

Dong-Ryeol Oh, Jong-In Kim, Min-Jae Seo, Jin-Gwang Kim, and Seung-Tak Ryu, “A 6-bit 10-GS/s 63-mW 4x TI time-domain interpolating flash ADC in 65-nm CMOS,” IEEE ESSCIRC, 2015.

Ba-Ro-Saim Sung, Dong-Shin Jo, Il-Hoon Jang, Dong-Suk Lee, Yong-Sang You, Yong-Hee Lee, Ho-Jin Park, Seung-Tak Ryu, “A 21fJ/conv-step 9 ENOB 1.6GS/s 2x Time-Interleaved FATI SAR ADC with Background Offset and TIming-Skew Calibration in 45nm CMOS,” IEEE ISSCC, 2015.

Hyeok-Ki Hong, Hyun-Wook Kang, Dong-Shin Jo, Dong-Suk Lee, Yong-Sang You, Yong-Hee Lee, Ho-Jin Park, Seung-Tak Ryu, “A 2.6b/cycle-Architecture-Based 10b 1.7GS/s 15.4mW 4x-Time-Interleaved SAR ADC with a Multistep Hardware-Retirement Technique,” IEEE ISSCC, 2015. 

Ji-Wook Kwon, Dong-Hwan Jin, Hyeon-June Kim, Sun-Il Hwang, Min-Chul Shin, Jong-Ho Kang, and Seung-Tak Ryu, “A Two-step 5b Logarithmic ADC with Minimum Step-size of 0.1% Full-scale for MLC Phase-Change Memory Readout,” IEEE CICC 2014. (Intel CICC Student Scholarship Award)

Hyeon-June Kim, Dong-Shin Jo, Jun-Hyeok Yang, and Seung-Tak Ryu, “A Low-Power Fast Readout Circuit using a Dual-Mode Sensing Algorithm for Medium-Size Capacitive Touch Screen Panels,” SID 2014, San Diego.

Ghil-Geun Oh and Seung-Tak Ryu,  “A dual channel 10-b pipelined ADC for Intelligent Transport System,” IEEE International Conference on Electron Devices and Solid-State Circuits, 2014.

Young-Sub Yuk, Seungchul Jung, Hui-Dong Gwon, Sukhwan Choi, Si Duk Sung, Tae-Hwang Kong, Sung-Wan Hong, Jun-Han Choi, Min-Yong Jeong, Jong-Pil Im, Seung-Tak Ryu, Gyu-Hyeong Cho, “An Energy Pile-Up Resonance Circuit Extracting Maximum 422% Energy from Piezoelectric Material in a Dual-Source Energy-Harvesting Interface,” IEEE ISSCC 2014. 

Ba-Ro-Saim Sung, C. K. Lee, W. Kim, J. I. Kim, H. K. Hong, G.G. Oh, C.H. Lee, M. Choi, H.J. Park, and S.T. Ryu, “A 6 bit 2 GS/s flash-assisted time-interleaved (FATI) SAR ADC with background offset calibration,” IEEE ASSCC, 2013.

S.-W. Hong, S. Jung, C. Park, T.-H. Kong, M.-Y. Jung, S.-T. Ryu and G.-H. Cho, “High-Gain Wide-Bandwidth Capacitor-Less Low-Dropout Regulator with Zero Insertion Utilizing Frequency Response of Inner Loops,” IEEE Symposium on VLSI Circuits 2013. 

Hyeok-Ki Hong, Hyun-Wok Kang, Barosaim Sung, Choong-Hoon Lee, Michael Choi, Ho-Jin Park, and Seung-Tak Ryu, “An 8.6 ENOB 900MS/s time-interleaved 2b/cycle SAR ADC with a 1b/cycle reconfiguration for resolution enhancement,” IEEE ISSCC, 2013.

Hyun-Sik Kim, Jun-Hyeok Yang, Sang-Hui Park, Seung-Tak Ryu, and Gyu-Hyeong Cho, “A 5.6mW inter-Channel DVO 10b Column-Driver IC with Mismatch-Free Switched-Capacitor Interpolation for Mobile Active-Matrix LCDs,” IEEE ISSCC, 2013.

Jun-Hyeok Yang, Sang-Hui park, Jung-Min Choi, Hyun-Sik Kim, Chang-Byung Park, Seung-Tak Ryu, and Gyu-Hyeong Cho, “A Highly Noise-Immune Touch Controller Using Filtered-Delta-Integration and a Charge-Integration Technique for 10.1-inch Capacitive Touch-Screen Panels,” IEEE ISSCC, 2013.

So Young Kang, Dongmin Kang, Hi Yuen Song, Hyunseok Choi, Inn Yeal Oh, Seung Tak Ryu, and Chul Soon Park, “A Direct Down Converted Low-Jitter Band Pass Delta Sigma Receiver with Frequency Translating Technique and Sinusoidal RF DAC,” Asia-Pacific Microwave Conference, 2012.

Hyeok-Ki Hong, Wan Kim, Sun-Jae Park, Michael Choi, Ho-Jin Park, and Seung-Tak Ryu, “A 7b 1GS/s 7.2mW nonbinary 2b/cycle SAR ADC with register-to-DAC direct control,” IEEE CICC, 2012.

Jong-Pil Im, Se-Won Wang, Young-Jin Woo, Young-Sub Yuk, Seung-Tak Ryu, and Gyu-Hyeong Cho, “A 40mV Transformer-reuse Self-startup Boost Converter with MPPT Control for Thermoelectric Energy Harvesting,” IEEE ISSCC, 2012.

Hyun-Sik Kim, Sang-Wook Han, Jun-Hyeok Yang, Sunil Kim, Young Kim, Sangwook Kim, Dae-Kun Yoon, Jun-Su Lee, Jae-Chul Park, Younghun Sung, Seong-Deok Lee, Seung-Tak Ryu, and Gyu-Hyeong Cho, “A Sampling-based 128 x 128 Direct Photon-counting X-ray Image Sensor with 3 Energy-Bins and Spatial Resolution of 60μm/pixel,” IEEE ISSCC, 2012.

Jong-In Kim, Wan Kim, Barosaim Sung and Seung-Tak Ryu, “A time-domain latch interpolation technique for low power flash ADCs,” IEEE CICC, 2011.

Ji-Wook Kwon and Seung-Tak Ryu, “An Inherently dB-linear Variable Gain Amplifier with Wideband Signal Bandwidth,” TriSAI 2011, Korea.

Chang-Kyo Lee, Ji-Wook Kwon, Sang-Hyun Cho and Seung-Tak Ryu, “An LDO-based supply referencing 10b 32MS/s pipelined ADC,” IEEE MTT-S IMWS-IRFPT, 2011.

Dong-Shin Jo and Seung-Tak Ryu, “A 0.4V 6.5nW 10b 2.5kS/s asynchronous SAR ADC,” IEEE MTT-S IMWS-IRFPT, 2011.

H. S. Kim, J. Y. Jeon, S. W. Lee, J. H. Yang, S. T. Ryu, and G. H. Cho, “A 0.014mm2 9b Switched-Current DAC for AMOLED Mobile Display Drivers,” IEEE ISSCC, 2011.

Sang-Hyun Cho, Chang-Kyo Lee, Jong-Kee Kwon, and Seung-Tak Ryu, “A 550µW 10b 40MS/s SAR ADC with multistep addition-only digital error correction,” IEEE CICC, 2010.

J.H.Yang, S. C. Jung, Y. J. Woo, J. Y. Jeon, S. W. Lee, C. B. Park, H. S. Kim, S. T. Ryu and G. H. Cho, “A Novel Readout IC with High Noise Immunity for Charge-Based Touch Screen Panels,” IEEE CICC, 2010.

So Yong Kang, Seung Tak Ryu and Chul Soon Park, “A CMOS programmable gain amplifier with constant current-density based trasconductance control,” IEEE CSICS, 2010.

Huy-Binh Le, Sang-gug Lee and Seung-Tak Ryu, “A regulator-free 84dB DR audio-band ADC for compact digital microphones,” IEEE ASSCC, 2010.

C.B.Park, Kiduk Kim, Sungwoo Lee, Gyusung Park, Seungtak Ryu, and Gyuhyung Cho, “A 10b linear interpolation DAC using body-transconductance control for AMLCD column driver,” IEEE ASSCC, 2010.

S.-H. Cho and S.-T. Ryu, “A Power Efficient Conversion Technique for SAR ADC,” TriSAI 2009, Japan.

C.-K. Lee, S.-H. Cho, and S.-T. Ryu, “A Reference-driver free ADC architecture,” TriSAI 2009, Japan.

Ba Ro Saim Sung, Sang-Hyun Cho, Chang-Kyo Lee, Jong-In Kim, and Seung-Tak Ryu, “A Time-Interleaved Flash-SAR Architecture for High Speed A/D Conversion,” IEEE ISCAS, 2009.

Jong-In Kim and Seung-Tak Ryu, “A Fully Differential Rail-to-Rail Input Dynamic Latch," ITC-CSCC, 2009.

Woo-Young Kim, Ki-Young Kim, Seung-Tak Ryu, Jae-Kil Jung and Chul-Soon Park, “1-bit and Multi-bit Envelope Delta-Sigma Modulators for CDMA Polar Transmitters,” APCM, 2008.

Gil-Seop Park and Seung-Tak Ryu, “A CMOS Linear Preamplifier Design for Electret Microphones,” ISOCC, 2008.

H. N. Nguyen, Y. S. Jang, Y. S. Son, S. T. Ryu and S. G. Lee, “A Multi-bit/cycle 12-bit Cyclic DAC for TFT-LCD Column Drivers," International Display Workshop (IDW), 2008.

Seung-Tak Ryu, Bang-Sup Song, Kanti Bacrania, “A 10b 50MS/s pipelined ADC with opamp current reuse,” IEEE ISSCC, 2006.